module mult_8bit_comb ( input [7:0] a, b, output reg [15:0] product ); always @(*) begin product = a * b; // Synthesized into LUTs or DSP slices end endmodule : Minimal code, fast simulation. Cons : No control over architecture; may waste resources on FPGAs if not using DSP slices.
Run with:
module booth_multiplier_8bit ( input signed [7:0] a, b, // signed 8-bit inputs output signed [15:0] product ); reg signed [15:0] pp [0:3]; integer i; always @(*) begin // Radix-4 Booth encoding of B // Simplified example: actual impl requires recoding logic for (i = 0; i < 4; i = i + 1) begin case (b[2*i+1], b[2*i], b[2*i-1]) // ... booth encoding cases default: pp[i] = 16'sb0; endcase end product = pp[0] + pp[1] + pp[2] + pp[3]; end endmodule 8bit multiplier verilog code github
module multiplier #(parameter WIDTH = 8) ( input [WIDTH-1:0] a, b, output [2*WIDTH-1:0] product ); assign product = a * b; endmodule For signed, use signed keyword: module mult_8bit_comb ( input [7:0] a, b, output
: Educational FPGAs (like BASYS 3 or DE10-Lite), resource-constrained designs without DSP slices. Verilog Implementation #3: Sequential (Pipelined) Multiplier Best for low-area designs where speed is not critical. The multiplication takes 8 clock cycles. booth encoding cases default: pp[i] = 16'sb0; endcase